The present technology relates to a semiconductor device and an electronic device, and more particularly, to a semiconductor device and an electronic device, which are capable of providing a sophisticated solid state imaging element while maintaining a high accuracy of a wire bonding process.
Generally, in a solid state imaging element, a photoelectric conversion unit is disposed in an imaging region at the center of a chip, a circuit unit is disposed in the periphery thereof, the periphery thereof is a chip edge region, and a plurality of wire bonding pad electrodes including an aluminum (Al)-based alloy film (for example, aluminum copper) for an external interconnection are disposed on the chip edge region.
The surface of the wire bonding pad electrode is covered with an insulating film or the like, but a metallic surface of the wire bonding pad is exposed as the insulating film or the like is opened.
In an assembly process of a semiconductor device, in order to electrically connect a semiconductor chip with a package, a wire bonding process of connecting an exposed metallic surface (pad electrode) on the semiconductor chip with an inner lead of the package using a metallic wire is performed.
Here, when a solid state imaging element is manufactured, a ball bonding technique is widely used as a wire bonding process, and pressure bonding is performed using a bonding wire made of gold (Au) such that a certain amount of load, heat, and ultrasonic vibration when an ultrasonic wave is used in combination are applied to a wire. At this time, in the solid state imaging element, for example, a heating temperature is set to be 250° C. or less on a chip in view of heat resistance of a material for a color filter to be mounted.
In the wire bonding process, a tool called a capillary is used, and a gold (Au) ball is pressure-bonded by moving the capillary to the position directly above an opened wire bonding pad and then moving the capillary down. At this time, the shape of the opened pad significantly affects the accuracy of the wire bonding process.
When the surface of the wire bonding pad is present at the deep position from the surface of the semiconductor chip, since the distance by which the capillary is moved down increases, the accuracy of the wire bonding process is lowered. For this reason, when the surface of the wire bonding pad is present at the deep position from the surface of the semiconductor chip, pressure bonding misregistration, a wire disconnection defect, or the like is likely to occur. Further, dust or moisture generated due to dicing is likely to remain, and a risk of pad corrosion (external appearance defect) also increases.
In recent years, from a point of view of power consumption, MOS types such as a complementary metal oxide semiconductor (CMOS) are widely used as a solid state imaging element mounted in a mobile device such as a mobile telephone with a camera or a personal digital assistant (PDA).
Further, as a MOS type solid state imaging element, in order to achieve high sensitivity, low noise, and high quality characteristics, a bottom-emission solid state imaging element having a structure in which light is emitted from a back side of a silicon (Si) substrate rather than a top-emission structure in the related art has been developed as a pixel structure.
However, in the top-emission structure in the related art, the depth of the wire bonding pad is 2 μm or less, and in the MOS type bottom-emission solid state imaging element, the depth of the wire bonding pad is 5 to 8 μm. Thus, the accuracy of the wire bonding process is lowered, and a process margin decreases. As a result, an occurrence risk of a characteristic defect or deterioration of reliability of a wire bonding increases.
In addition, in recent years, as a more than more technique, substrate stacking (3D device) has been leading the semiconductor industry. Here, as a next generation bottom-emission solid state imaging element, a bottom-emission solid state imaging element having a stacked structure, which is a leading product of a high-functional 3D device, has been developed, and mass production thereof is expected.
However, in the bottom-emission type having a stacked structure, the position of the wire bonding pad is 12 μm or more which is deeper than in the bottom-emission type, and deeper than in products in the related art. For this reason, it is becoming more technically difficult to form a wire bonding directly on a pad.
In this regard, a technique in which an electrode used to perform wire bonding is exposed to the chip surface has been proposed (for example, see JP 2011-192669 A). In the technique disclosed in JP 2011-192669 A, in a dicing region on which a pad, a bonding wire, a laser melting groove, and a dicing groove are arranged, the pad is formed on an anti-reflection film and electrically connected to an interconnection layer formed in an inter-layer insulating film.